Constrained random test pattern generation entered the scene a couple of decades ago as a better way to spend time and resources for the creation of stimulus. Stimulus definition had become an arduous ...

The huge undertaking of verifying a system-on-chip (SoC) design has challenged engineers for more than 20 years –– the amount of time spent on it hasn’t varied much from between 50-70% of the entire ...

PARTNER CONTENT: Given the size and complexity of modern semiconductor designs, functional verification has become a dominant phase in the development cycle. Coverage lies at the very heart of this ...

This blog talks about challenges and solutions while reusing the required functional coverage of IP at the SoC level, coverage merging issues, exclusion/removal of groups from functional coverage ...

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based ...